: Synplify, Vivado, XILINX ISE, Work experience in Xilinx FPGA based design implementation. FPGA RTL coding(Verilog/VHDL.../System Verilog), FPGA constraint setup, verification, synthesis, par and timing closure. Hands-on experience in WIFI...
is a plus. Programming/scripting: MATLAB and/or C++; Python for automation and data analysis preferred. Basic familiarity with HDLs (Verilog.../VHDL) and co-simulation concepts. Comfortable with data analysis, plotting, and writing clear, concise technical reports...
Verilog, and VHDL coding practices. Experience in UVM Verification framework, Assertion based Verification, Code coverage.... Here's what we are looking for with this role: Essential Requirements Experience: 3-5 years in FPGA systems design and verification with Verilog coding, System...
especially using System Verilog Have knowledge of firmware and RTL design (VHDL/Verilog) Ideally have knowledge of Cadence... Verification Methodology (UVM) draw on test scenarios using System Verilog verify functionality using the Constrained Random...
. Design And Architect Large-Scale Rtl Design Solutions Using Vhdl And Verilog, Ensuring Scalability, Performance, And Security... Requirements 1. Expert Knowledge Of Rtl Design Principles And Practices. 2. Proficiency In Vhdl, Verilog, And Systemverilog...
: We are looking for an experienced FPGA RTL Design Engineer with strong expertise in VHDL and high-speed packet processing. The candidate will work... and implement RTL using VHDL Perform functional verification, linting, synthesis, and timing closure Validate FPGA designs...
Epergne Solutions ⚡⚡ Fri, 05 Jun 2026 04:59:22 GMT
Engineers design and develop digital hardware blocks using HDLs such as Verilog/SystemVerilog/VHDL for ASIC or FPGA projects... and silicon bring-up Skill Requirements Verilog/SystemVerilog/VHDL Digital design fundamentals FSMs, pipelines, memories...
Design Engineers design and develop digital hardware blocks using HDLs such as Verilog/SystemVerilog/VHDL for ASIC or FPGA... FPGA prototyping and silicon bring-up Skill Requirements Verilog/SystemVerilog/VHDL Digital design fundamentals...
FPGA Design/Zebu Engineer (Senior/Lead/Staff)
: Synplify, Vivado, XILINX ISE, Work experience in Xilinx FPGA based design implementation. FPGA RTL coding(Verilog/VHDL.../System Verilog), FPGA constraint setup, verification, synthesis, par and timing closure. Hands-on experience in WIFI...
Qualcomm ⚡ ⚡ Wed, 10 Jun 2026 07:11:40 GMT