FPGA IP Design and Verification Engineer
languages (VHDL, Verilog, SystemVerilog). Experience or knowledge in scripting languages such as Tcl, Perl, or Python. Prior...: FPGA IP Design & Validation using Verilog. Support the FPGA post-silicon system validation group in ongoing and upcoming...
Staff Design Evaluation Engineer
. Strong programming skills in Python, C, C#, and VHDL/Verilog for automation, debug, and validation. Hands‑on experience with bench...
Analog Devices ⚡ ⚡ Thu, 16 Apr 2026 03:06:16 GMT