senior engineer- DV
(OVM/UVM). Good in concepts Code coverage and functional coverage. Expertise in Verilog and / or VHDL is desired... etc. Working on full chip verification and OVM/UVM Methodology, System Verilog is a must with 3+years of recent work experience...
R&D Engineering, Staff Engineer (C/C++, Data Structures, Algorithm, RTL compiler)
with complex languages like Verilog and VHDL, and the challenge of keeping up with both the theory and the practical quirks of real... grounding in parsing, elaboration, control and data flow analysis, and logic synthesis. Strong knowledge of Verilog and VHDL...
Synopsys ⚡ ⚡ Wed, 06 May 2026 00:52:55 GMT