Lead Application Engineer – Digital Verification
in hardware design and/or verification methodologies. Solid hands‑on verification experience using UVM, SystemVerilog, Verilog..., VHDL, SystemC, and SystemVerilog Assertions (SVA). Hands‑on experience with Cadence Verification IP or Jasper...
Lead Application Engineer – Digital Verification
in hardware design and/or verification methodologies. Solid hands‑on verification experience using UVM, SystemVerilog, Verilog..., VHDL, SystemC, and SystemVerilog Assertions (SVA). Hands‑on experience with Cadence Verification IP or Jasper...
Cadence Design Systems ⚡ ⚡ Sat, 30 May 2026 01:35:58 GMT