R&D Engineering, Sr Staff
in hardware partitioning, emulation, or hardware-assisted verification. Strong proficiency in RTL design (Verilog, SystemVerilog..., or VHDL) and logic synthesis flows. Deep understanding of partitioning algorithms, resource allocation, and hardware/software...
R&D Engineer, Sr Staff
, and collect. Experience with scripting languages (Perl, Tcl, Shell, Python) and familiarity with HDL (System Verilog/VHDL...
Synopsys ⚡ ⚡ Fri, 27 Feb 2026 07:46:01 GMT