within an interdisciplinary R&D environment Preferred (Asset but not required) Experience with ASIC design flows, RTL, Verilog/VHDL... of macromodels or behavioral models (e.g., Verilog-A) for system-level simulation Embedded Systems and Software Development...
DSP - Optical Design Engineer
GitHub. Familiarity with Verilog or VHDL is a plus. Team player with a mindset focused on the successful delivery of the...
Celero Communications, Inc. ⚡ ⚡ Thu, 13 Aug 2026 04:14:44 GMT