, Verilog and/or VHDL) design or verification 4+ years of experience in Software programming or scripting (e.g. C/C...++ and/or Python) Preferred Qualifications: 6+ year of experience with IP Integration, RTL Design, SystemVerilog, Verilog...
Altera ⚡ $98900 - 143000 per year ⚡ Tue, 31 Mar 2026 04:37:25 GMT
FPGA Development Tools Engineer
, simulation) Experience with HDL languages such as Verilog and/or VHDL Other good skills/knowledge to have: Experience...
Altera ⚡ ⚡ Sun, 19 Apr 2026 22:53:34 GMT