Engineering or similar Experience with hardware description languages, Verilog (preferred) or VHDL Familiarity with verification..., including System Verilog simulation and formal verification in a UVM environment Support and follow through on validation...

Verilog or VHDL Hands‑on experience with synthesis, timing constraints, and static timing analysis (STA) Practical...

) or VHDL Familiarity with verification of digital and / or mixed signal circuits, e.g. System Verilog test benches... methods, including System Verilog simulation and formal verification in a UVM environment Support and follow through...

, Verilog/VHDL, or hardware verification concepts Familiarity: Requirements and traceability tooling (e.g., Polarion, Jama...

development. Basic familiarity with FPGA development (VHDL, Verilog, or HLS) is a plus. Ability to work within technically...