ASIC/FPGA Design and Verification Engineer – Space Electronics - MTV (Associate, Experienced, or Lead)
Experience with ASIC/FPGA design or verification Experience with Register Transfer Language - e.g. Verilog, VHDL, SystemVerilog... languages: System Verilog, System Verilog Assertions Ability to executable test plans Proficiency with Object Oriented...
Applications Engineering, Sr Engineer
Proficiency in SystemVerilog, UVM, SVA, and HDL languages like Verilog and VHDL, with the ability to read and debug complex...
Synopsys ⚡ $109000 - 163000 per year ⚡ Wed, 02 Sep 2026 00:28:34 GMT